1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the semiconductor device, and is applied, for example, to a MOS (metal-oxide semiconductor) transistor, in which the mobility of carriers is varied by applying a stress to a channel region, and a method of manufacturing the same.
2. Description of the Related Art
It is conventionally known that if a stress is applied to a channel region of Si (silicon) or SiGe (silicon germanium), the mobility of carriers varies. If a compressive stress is applied to the channel region, the mobility of holes increases. On the other hand, if a tensile stress is applied to the channel region, the mobility of electrons increases. In order to take advantage of this phenomenon and to produce a desired stress, various attempts have been made. For example, process conditions are altered, or dimensions of structural parts of the device are altered (see, e.g. Jpn. Pat. Appln. KOKAI Publication No. 6-232170). Typical examples of the semiconductor device using this phenomenon are as follows.
1. A semiconductor device including an Si3N4 (silicon nitride) film as a liner insulation film, the thickness of the Si3N4 film being varied to control the magnitude of stress.
In this structure, the value of stress that is to be applied varies due to non-uniformity in thickness of the Si3N4 film that is deposited, and the controllability of stress deteriorates. In the case of applying this technique to both PMOS and NMOS transistors, it is necessary to form different Si3N4 films for applying a compressive stress and a tensile stress. This requires provision of an expensive manufacturing apparatus, leading to an increase in manufacturing cost.
2. A semiconductor device to which a so-called strain Si substrate is applied.
In this structure, crystal defects tend to easily occur in the strained Si of the channel region, and thus a junction leak tends to easily occur. The strained Si substrate is fabricated by successively and epitaxially growing a stacked structure of an Si buffer layer/SiGe layer/stained Si layer on an Si substrate. Consequently, the number of fabrication steps increases, and a manufacturing cost becomes much higher than in the case of ordinary Si substrates.